A Page-Buffer and Fail-Bit Counter-Based In-Memory Computing Platform for 3-D NAND Flash Memory

We propose an in-memory computing platform for 3D NAND Flash memory. By re-purposing the existing page buffers and fail-bit counters in the NAND Flash chip, diverse in-memory computing applications such as bulk bitwise operation, in-memory search, and vector similarity search can be realized. The re-design cost is minimized, and its operation is almost comparable to the original NAND Flash’s program, erase, and read operations. It is robust against process, voltage, and temperature variations. By reducing the need for huge and frequent data transfers between storage and the processor, latency and energy efficiency are greatly improved. This design presents an attractive and promising option for in-memory computing applications in NAND Flash memory. Furthermore, it can be applied to other storage or memory devices that possess the page buffers and fail-bit counters suitable for re-purposing.