Variation-Tolerant Circuit Design and Online Learning Framework for Memristor-Based Trace-STDP SNN

Spiking neural networks (SNNs) demonstrate significant potential for energy-efficient neuromorphic computing, while trace-based spike-timing dependent plasticity (trace-STDP) serves as a biologically inspired learning rule to improve SNN temporal learning. Memristor-based implementations of trace-STDP SNN leverage device non-linearity to emulate synaptic dynamics, enabling highly energy-efficient computation. However, the mapping from trace-STDP to memristor arrays introduces inherent variations, which significantly degrade network accuracy, posing a critical challenge for the reliable deployment of memristor-based neuromorphic systems. To address this issue, efficient variation-tolerant strategies are essential. However, current approaches do not take the trace-STDP SNN characteristics into consideration, thereby limiting their algorithm-and hardware-level effectiveness. In this work, a variation-aware online learning framework for memristor-based trace-STDP SNN is proposed, with hierarchical simulations integrated across software, ASIC, memristor-array, and memristor-device levels. Through variation analysis experiments, it is observed that variations in near-zero trace values significantly impact network accuracy. To mitigate these effects, a tailored variation-tolerant strategy is developed, together with a configurable hardware clipping unit and an ASIC/memristor co-simulator. The proposed variation-tolerant design achieves up to a 16.97% accuracy improvement, with only a 0.02% extra power overhead and a 0.01% extra area overhead, while a parallel design ensures no additional latency overhead. Integrating the co-simulator into the proposed framework facilitates design space exploration, enhancing the robustness and efficiency of memristor-based neuromorphic computing.