NMPHDC: A 12-nm Reconfigurable Multi-Port SRAM-Based Near-Memory Hyperdimensional Computing Architecture

Hyperdimensional Computing (HDC) is a brain-inspired computing paradigm that represents information using high-dimensional vectors, referred to as hypervectors (HVs), enabling inherent robustness to noise and efficient learning on resource-constrained platforms. In this work, we present NMPHDC, a reconfigurable multi-port (MP) SRAM-based logic-near-memory (LnM) HDC architecture that supports on-chip training and inference. The proposed design is configurable across multiple HV dimensions, including 256, 512, and 1024 bits, enabling flexibility across diverse workloads. A lightweight custom LnM block enables LnM execution of key HDC operations, including XOR for binding and majority (MAJ) for bundling, significantly reducing data movement overhead. In addition, we propose a custom on-chip training algorithm and integrate a dedicated on-chip random number generator (RNG) to strengthen training security through locally generated HVs. A centralized HDC controller orchestrates dataflow, computation, training, and testing with seamless configurability. Implemented in GlobalFoundries (GF) 12nm low-power (LP) FinFET technology, NMPHDC occupies 1.25 mm2, consumes ∼0.72 mW in standby and ∼19.7 mW at 100 MHz, and achieves classification accuracies of 93.33%, 25.75%, 72.62%, and 75.18% on the ECG5000, CIFAR-10, MNIST, and ISOLET datasets, respectively.