Photolithography-Compatible Low-Voltage OTFT Enabled by a Trilayer Dielectric Design With PDK-Compatible Development

Organic thin-film circuit design requires not only high-performance transistors but also reproducible device behavior that can be captured in compact models and supported by a process design kit (PDK). Existing low-voltage OTFT technologies often rely on shadow-mask or printed process, where coarse patterning and alignment variability hinder device uniformity, parasitic management, and integration scalability. This work presents a photolithography-compatible OTFT platform based on a tri-layer dielectric stack that achieves uniform, low-voltage transistor operation with a mobility of 0.87 ± 0.07 cm2V−1s−1, a threshold-voltage of 0.96 ± 0.13 V and an 87% functional yield across the substrate. These reproducible device characteristics enable the extraction of a calibrated Level-62 RPI poly-TFT compact model, which is integrated into a complete PDK with defined layers, routing modules, and verified DRC/LVS rules. Circuit demonstrations, including inverters, NAND gates, a master-slave D-flip-flop, and a full adder, reproduce the expected Boolean functionality under low-voltage operation. The results establish a unified workflow that links lithography-defined OTFT fabrication with PDK-compatible modeling and circuit-level simulation, providing a foundation for scalable organic thin-film electronics.