A Hardware Efficient Near Sensor Computing Architecture for Gait Analysis: Utilizing Alpha Max Approximation and Wallace Tree Synthesis
Abstract
The growing demand for energy-efficient electronic wearable devices with the capability of performing real-time gait analysis is leading to the necessity of low-power hardware that is able to analyse the wearer’s gait in real-time. In this paper, a complete very large-scale integration (VLSI) implementation of a pedometer application-specific integrated circuit (ASIC) is presented, which is suitable for long-term recording of physical activities in hybrid flexible-rigid sensor nodes. The system architecture integrates an ADXL micro-electro-mechanical systems (MEMS) accelerometer with a motion-sensing unit and an OLED display for user feedback, all powered by a custom processing core. To reduce the computational load, the architecture employs a hardware-efficient Alpha-Max Beta-Min algorithm for vector magnitude approximation and a recursive moving average filter for noise elimination. Based on 90 nm complementary metaloxide-semiconductor (CMOS) technology at the standard real-time-clock (RTC) frequency of 32.768 kHz, the physical layout was carried out using the Cadence digital suite with Multi-Mode Multi-Corner (MMMC) timing analysis and Non-Default Routing (NDR) rules (2W2S) for clock tree signal integrity. Synthesis outputs show that Wallace Carry-Save Adder (CSA) structures were automatically inferred, shortening the critical path delay by 3.76×. The final GDSII layout achieves a core area of 9,553 μm2with 953 gate instances and ultra-low power consumption of 50.01 μW, with leakage power the dominant contributor at 99.3% due to the extremely low operating frequency. Post-layout analyses show battery-friendly operation with an estimated lifetime exceeding 18 months on a standard CR2032 coin cell at 33.3 μJ per detected step. The design is sign-off clean with zero Design Rule Check (DRC), Layout Versus Schematic (LVS), and geometry violations, featuring a clock tree with 6 ps skew across 200 flip-flops. Step detection is validated at 98.6% system-level accuracy (Precision = 99.0%, Recall = 99.6%, F1-Score = 99.3%) across five gait scenarios.
Fields of Study & Subjects
Gait Recognition and Analysis
Balance
Gait
and Falls Prevention
Robotic Locomotion and Control
Publication details
- Journal / source
- IEEE Journal on Flexible Electronics
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Pages
- 1–1
- Publication date
- 1 January 2026