Hardware Optimization Methods for High-Speed Electrical Impedance Tomography System

Electrical impedance tomography (EIT) is an advanced visualization modality. In recent years, high-speed devices are commonly employed in EIT systems to accomplish complex tasks and enhance the real-time capability. Signal integrity (SI) and power integrity (PI) are major concerns in the high-speed system design. However, SI/PI issues have received limited attention due to their negligible impact on early developed low-speed EIT systems. The hardware performance degradation introduced by SI/PI issues gradually emerges in the high-frequency range, which may degrade the SNR of the EIT system and aggravate the image distortion caused by the inherent ill-posed problem of the EIT technique. This study comprehensively analyzes the major causes of SI/PI issues in the high-speed EIT systems and proposes the corresponding hardware optimization methods. The proposed methods are applied to a practical EIT system to validate their effectiveness. Experimental results illustrate that the SI/PI issues are effectively mitigated. The average signal-to-noise ratio (SNR) of the EIT system is improved by 5.4dB and the imaging quality is generally enhanced. The methods proposed in this study offer a low-cost, supplementary approach to improve the hardware performance of the high-speed EIT systems.