An 11.95-ENOB 560-MS/s Amplifier-Switching Subranging Analog-to-Digital Converter With Multi-Threshold Comparators

This article proposes a 14-bit, 560-MS/s subranging analog-to-digital converter (ADC) that employs an amplifier-switching architecture with multi-threshold comparators. The proposed amplifier-switching architecture reuses a flash quantizer multiple times during subranging conversion by amplifying the residue voltage with an appropriate gain at each quantization step. This approach reduces the required number of comparators, thereby lowering hardware complexity and improving power efficiency. The proposed multi-threshold comparator enables multi-level decision using a single differential input stage, which reduces input capacitance, kickback, and power consumption. The proposed ADC, fabricated in a 28-nm bulk CMOS process, achieves measured SNDRs of 73.7 and 72.2 dB at 560 MS/s for low and Nyquist input frequencies, respectively, with a power consumption of 9.76 mW. This results in a Schreier figure of merit (FoM) of 176.8 dB at Nyquist.