Side-Channel Attack-Resistant HMAC-SHA256 Accelerator With Boolean and Arithmetic Masking in Intel 4 CMOS

This work describes a side-channel attack (SCA)-resistant hash-based message authentication code (HMAC) accelerator with secure hash algorithm 2 (SHA-2) using Boolean and arithmetic masking along with the first-reported ASIC implementation in Intel 4 CMOS with 10 M measured traces. Previously reported masked datapath suffers from high area/performance overheads (>100%) designs due to non-linear Boolean operations, arithmetic additions, and mask conversions and lack rigorous attack characterization with measured traces. This work introduces an SCA-resistant Boolean/arithmetic masked HMAC-SHA256 accelerator fabricated in Intel 4 CMOS occupying 2455$\mu $m2, delivering 1.7-Gb/s (3.4-Gb/s) output hash (input message) throughput and energy efficiency of 6.1 pJ/b at 750 mV and$25~^{\circ }$C. The proposed SCA-resistant HMAC-SHA256 design features: 1) multiplexer-based masked non-linear (MajandCh) compression circuits providing up to 67% reduction in delay and area; 2) Boolean-to-arithmetic (BtoA) mask conversion integrated with carry-save adder (CSA) gates resulting in$2.4\times $lower delay overhead; 3) secure arithmetic-to-Boolean (AtoB) mask conversion achieving$3.3\times $lower area overhead using sparse-tree adder topology composed with multiplexer-based masked gates; 4) SCA resilience demonstrated with minimum-trace-to-disclosure (MTD) of 10 M and 6.4 M power/EM traces against test vector leakage assessment (TVLA) and correlation power analysis (CPA) resulting in$\gt 73\times $higher SCA resistance compared to unprotected engine; and 5) 17%/$2.4\times $lower area/performance overheads compared to previously reported implementations.