A 94-fs Jitter and −249.3-dB FoM MDLL With Background Calibration of Injection Phase and Slew-Rate Mismatch

This article presents a ring oscillator (RO)-based multiplying delay-locked loop (MDLL) that incorporates a dual-background calibration scheme to compensate for both injection phase and slew-rate mismatches. The MDLL employs the proposed frequency/slew-rate detector (FSD) to distinguish both mismatch types by comparing the pulse widths of consecutive output clock cycles before and after injection. Two independent feedback loops separately adjust the RO frequency and injection slew rate through an RO and a transition slew-rate controller (TSC), respectively. For accurate mismatch detection, the FSD includes an internal calibration loop that removes offset caused by internal path mismatches. Fabricated in 40-nm CMOS, the MDLL occupies 0.045 mm2and consumes 13.3 mW at 4-GHz output. It achieves integrated rms jitters of 94 and 89fs at 4 and 5GHz, respectively. With the proposed FSD, the reference spurs are reduced by approximately 30 dB, achieving measured spur levels of –54dBc at 4GHz and –50dBc at 5GHz.