A Bidirectional Neuromodulation Chipset With Algorithm-Aware AFE Optimization and High-Voltage-Compliant Stimulation

This work presents a bidirectional neuromodulation chipset with 64-channel neural analog front-end (AFE), and a four-channel current stimulator. The chipset employs a heterogeneous architecture, combining a 28-nm low-voltage (LV) CMOS process for the AFE and the digital backend (DBE) to improve area and power efficiency, with a 180-nm high-voltage (HV) bipolar-CMOS-DMOS (BCD) process for the stimulation driver to achieve HV compliance. An AFE–DBE co-design framework is proposed to relax AFE noise requirements without sacrificing classification performance in the DBE, thus enabling significant reductions in AFE’s area and power consumption. In addition, we introduce a novel embedded current-steering digital-to-analog converter (IDAC) structure that addresses key limitations of conventional IDACs in multichannel direct-digitization recording architectures, including noise degradation from IDAC switching, and channel-to-channel gain variations. Overall, the proposed chipset achieves HV compliance (10 V) in the stimulator, while maintaining exceptional area and power efficiency in the AFE and DBE. Notably, the AFE achieves the smallest per-channel area (0.0009mm2) and the lowest per-channel power (204nW) reported to date for electrocorticography (ECoG) acquisition (${\leq }1$kHz bandwidth). Together, these results highlight the chipset’s potential for implantable neuromodulation systems that enable long-term monitoring of neurological disorders with closed-loop intervention.