A 175-MHz BW 60-dB SNDR 6th-Order Bandpass Cascaded Time-Interleaved Noise Shaping SAR ADC
Abstract
The noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) architecture is very power efficient but limited in bandwidth (BW). Time-interleaving (TI) expands the NS SAR BW with low hardware cost, but the conventional noise transfer function (NTF) zero placement leads to a marginal BW improvement with increasing NTF order. This work proposes a new hybrid structure utilizing cascaded (Ca) NS to decouple the oversampling rate (OSR) from the NTF order. A 6th-order bandpass (BP) cascaded time-interleaved (CaTI) NS SAR implements complex conjugate NTF zeros and requires only three interleaved channels and an OSR of$4\times $. The prototype, fabricated in 28-nm CMOS, provides a 60-dB signal-to-noise-distortion ratio (SNDR) over a 175-MHz BW without calibration. The core circuit occupies 0.02 mm2and consumes 3.38 mW at 1.4 GS/s. The corresponding Schreier SNDR figure of merit (FoM) is 167 dB. The experimental results demonstrate that the proposed CaTI NS SAR is a more robust and efficient alternative to conventional TI NS SAR ADC.
Fields of Study & Subjects
Analog and Mixed-Signal Circuit Design
Radio Frequency Integrated Circuit Design
Advancements in PLL and VCO Technologies
Publication details
- Journal / source
- IEEE Journal of Solid-State Circuits
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Volume
- 61
- Issue
- 4
- Pages
- 1388–1399
- Publication date
- 27 January 2026