MixCIM: A Hybrid Computing-in-Memory Macro With Less Data-Movement and Better Memory-Reuse for Depthwise Separable Neural Networks

Computing-in-memory (CIM) architectures have demonstrated strong potential for edge artificial intelligence (AI) devices due to their enhanced parallelism and energy efficiency. With the growing complexity of AI tasks and the rapid increase in model size, computation and deployment costs have surged. Depthwise separable neural networks (DSNNs) have attracted interest for offering appreciable performance with far fewer parameters. However, the core operation in DSNNs, depthwise separable convolution (DSC), exhibits a different multiply-and-accumulate (MAC) pattern that conventional CIM macros are not optimized to handle efficiently. As a result, deploying DSC on conventional CIM platforms remains challenging. In this article, we propose MixCIM, a mixed macro that integrates computing-near-memory (CNM) and CIM. It achieves high energy efficiency for DSC computations through a mix-memory computing architecture. With a 2’s complement storage-sign magnitude computation (TCS-SMC) encoding, it reduces the activations’ movement and MAC energy. A slidable eDRAM array enhances the parallelism of DW convolution to improve throughput. A memory sharing scheme between input and output activations increases effective memory use. It optimizes complete DSC with both PW and DW convolutions, achieving superior energy efficiency. Measurement results show that the proposed 28-nm macro achieves 40.99 TOPS/W for pointwise convolution (PWC), 15.31 TOPS/W for depthwise convolution (DWC), and 17.2 TOPS/W for DSC, all at signed 8-bit inputs and weights. The accuracy on CIFAR-10 is 92.47% for MobileNet-V2.