A 60-GHz Low-Noise mmWave Divider-Less Fractional- N Cascaded PLL Achieving −250.2-dB FoM J in 28-nm CMOS

This article presents a fractional-${ {N}}$cascaded phase-locked loop (PLL) operating in the mmWave band from 55.8 to 64.2 GHz. The cascaded architecture consists of a first-stage fractional-${ {N}}$reference-sampling (RS) PLL and a second-stage sub-sampling (SS) PLL, incorporating two key innovations. The first-stage RS-PLL leverages a fully differential voltage-domain quantization-noise cancellation (FDVD-QNC) scheme to suppress the quantization noise of the delta–sigma modulator. The proposed FDVD-QNC, implemented through two sequential steps—bottom-plate voltage switching of the sampling capacitor and intentional offset voltage control of the transconductance cell—achieves a resolution of 0.08 mV with an integral nonlinearity (INL) within 1 LSB, while consuming only 0.64 mW. Moreover, its differential topology minimizes susceptibility to external noise sources and doubles the gain of the sampling phase detector (PD). As a result, the first-stage RS-PLL achieves$48.4~\text {fs}_{\text {rms}}$jitter and a fractional spur of −62.8 dBc with only 14.2 mW of power. Next, to enable reliable frequency acquisition in the second-stage SS-PLL, a frequency-locked loop (FLL) based on a switched-capacitor (SC) frequency-to-voltage converter (FVC) is proposed. The SC-FVC realizes a mmWave divider-less FLL by converting frequency into voltage, thereby eliminating the need for a bulky and power-hungry mmWave divider. The SC-FVC-based FLL consumes 0.84 mW and achieves frequency acquisition within 448 ns without harmonic lock in the SS-PLL. The cascaded PLL is fabricated in a 28-nm CMOS process and occupies an active area of 0.33 mm2. It achieves$58.4~\text {fs}_{\text {rms}}$jitter with 28.4 mW, corresponding to a$\text {FoM}\!_{\text {J}}$of −250.2 dB.