A 14-nm Nonvolatile-Volatile-Fused Compute-In-Memory Macro Based on Logic-Compatible Flash for Plastic Neural Networks

Designing computing-in-memory (CIM) chips with synaptic plasticity can potentially support energy-efficient on-chip learning in edge devices for rapid local task adaptation. Its silicon implementation is challenging as it requires hybridizing nonvolatile and volatile memory (VM) and customized computational operations. In this work, we propose a plastic CIM (P-CIM) macro featuring: 1) the logic-compatible flash (LF) cells in a standard 14-nm logic process that can be integrated with static random access memory (SRAM) cells in the same array; 2) the plastic cell array (PCA) that can perform matrix elementwise multiplication (MEM) followed by matrix-vector multiplication (MVM) in a single clock cycle; 3) the differential merged-into-array analog-to-digital converter (DMA-ADC) with capacitor reuse and a multielement sparsity-aware (MESA) scheme to reduce area and power consumption. A P-CIM macro integrating 32 k LF cells, 4 k SRAM cells, and 32 8-bit DMA-ADCs is fabricated in a 14-nm FinFET logic process. It achieves a peak energy efficiency (EF) of 22.64 TOPS/W for the MEM-MVM operations. It achieves computing accuracies of 78.04% on the Omniglot one-shot learning task and 89.65% on the CIFAR-10 pattern memorization task.