A 136.6-dB-DR 174.3-dB-FoM S Versatile Current-to-Digital Converter With a Truncated-Noise-Shaped Baseline-Servo-Loop

View at publisher
Authors: Taeryoung Seol, Sehwan Lee, Geunha Kim, Samhwan Kim, Yeonjae Shin, Jeongyoon Wie, Seungyeob Baik, Hongki Kang, Minyoung Song, Jong‐Hyeok Yoon, Junghyup Lee
Cited by: 0

Abstract

This article presents a high-resolution, wide dynamic-range (DR) current-to-digital converter (IDC) capable of directly digitizing a broad range of bio-current signals. To achieve high resolution, the IDC uses a second-order continuous-time delta–sigma modulator (CT-DSM) architecture with a low-noise current-recycling operational amplifier (op-amp) and a highly linear pseudo-differential voltage-controlled oscillator (VCO)-based quantizer. The IDC achieves a signal-to-noise-and-distortion ratio (SNDR) of 96.3 dB and a spurious-free dynamic range (SFDR) of 109.2 dB over a 4-kHz bandwidth while consuming$64.1~{\mu }$W, corresponding to a Schreier figure-of-merit (FoMS) of 174.3 dB. To extend the DR of the CT-DSM with minimal power and area overhead, a digital-intensive truncated-noise-shaped baseline-servo-loop (TNS-BSL) scheme is proposed. Fabricated in a$0.18~{\mu }$m CMOS process, the proposed IDC achieves a DR of 136.6 dB, corresponding to a maximum input range of$200~{\mu }$A.

Fields of Study & Subjects

Analog and Mixed-Signal Circuit Design Radio Frequency Integrated Circuit Design Advancements in PLL and VCO Technologies

Publication details

Journal / source
IEEE Journal of Solid-State Circuits
Volume
61
Issue
8
Pages
4154–4166
Publication date
27 January 2026
Language
영어