A 19.4-fs RMS Jitter 0.1-to-44-GHz Cryo-CMOS Fractional- N CP-PLL Featuring Automatic Bleed Calibration for Quantum Computing

Cryogenic fractional-$N$phase-locked loops (PLLs) are essential for large-scale superconducting quantum computing, and serve as integrated pump sources for Josephson parametric amplifiers. These PLLs enable high-fidelity qubit readout while reducing the thermal load and wiring complexity associated with room-temperature generators. However, the cryogenic pump sources developed thus far were unable to meet the stringent phase noise and frequency agility requirements for high-fidelity qubit readout. In this study, we present a cryo-CMOS fractional-$N$charge-pump PLL (CP-PLL) operating over a range of 4–300K that provides low-noise, multi-frequency pump and clock signals. We proposed an automatic bleed calibration (ABC) technique to mitigate the folding effect of the delta-sigma ($\Delta \Sigma $) modulator residue through phase-frequency detector (PFD) and CP nonidealities. This approach helps in detecting PFD pulsewidth asymmetry and digitally optimizing the bleed current, thereby minimizing both the reference and fractional spurs. The proposed prototype was fabricated via a 28-nm CMOS process and synthesizes signals ranging from 0.1 to 44 GHz using on-chip dividers and multipliers. At 4 K, it achieves integrated jitter (12 kHz–20 MHz) of 19.4 fs under a frequency of 8.6 GHz, with reference spurs below −71 dBc and fractional-spur suppression of up to 40 dB when ABC is enabled. At 300 K, the proposed CP-PLL achieves a jitter of 29.7 fs under a frequency of 8.6GHz with a reference spur of −82 dBc. To the best of our knowledge, this represents the lowest jitter reported for a cryo-CMOS fractional-$N$CP-PLL in the literature.