Dual-Mode Inverter-Based Write Termination Scheme for Energy- and Area-Efficient Write Operation in 28-nm 1T1MTJ STT-MRAM

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising non-volatile memory, but its write operation requires a large static current, leading to high write power. Resistance-monitoring write termination (RM-WT) schemes were introduced to reduce write power, but they suffer from several limitations: 1) the sensing circuit (SC) used in previous schemes has limited effective input voltage, degrading the robustness of WT; 2) the prior schemes cause severe area overhead due to the additional WT circuits besides sense amplifier (SA); and 3) the previous schemes cannot support write 0 termination, limiting write power reduction. This article proposes a dual-mode inverter-based write-termination (DMI-WT) circuit that resolves these limitations. In the proposed scheme, a single-ended inverter-based SC (INV-SC) is used, which doubles the effective input voltage without area overhead. In addition, self-referenced offset cancel (OC) is used, which enables robust WT and SA operation. DMI-WT enables WT operation for both write 0 and write 1 operation while simultaneously serving as an SA, thereby reducing the write power and removing the area overhead caused by WT circuits. A prototype chip fabricated in 28-nm CMOS technology with a 256-kb STT-MRAM array shows that DMI-WT achieves up to$6.39{\times }$area overhead reduction,$7.5{\times }$lower write power per bit at a 20-ns write access time,$1.27{\times }$faster read access time, and$1.41{\times }$lower read power compared with previous WT circuits using STT-MRAM.