A Low Phase Noise and High-Efficiency Biharmonic Class-F −1 VCO With Improved Waveform Shaping

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Authors: Yue Fei Wu, Yatao Peng, Jun Yin, Rui P. Martins, Pui‐In Mak
Cited by: 1
References: 41

Abstract

This article presents an inverse class-F (class-F−1) voltage-controlled oscillator (VCO) architecture that achieves a higher figure of merit (FoM) compared with the reported RF harmonic VCOs. The design conditions for FoM improvement in biharmonic VCOs (with sole 2nd harmonic) are analyzed. To meet the conditions revealed, a distributed dual-mode resonator (DMR) without magnetic flux cancellation, featuring simultaneously high 1st and 2nd harmonic impedances, is introduced to realize the proposed class-F−1VCO, enabling improved phase noise (PN) with reduced power consumption. The proposed structure is able to boost the 2nd harmonic voltage components while suppressing the detrimental misaligned 3rd harmonic voltage in the output waveforms by introducing significant 2nd harmonic voltage ($V_{\mathrm {G2}}$) at the gates. Consequently, the waveform exhibits an extended flat region of the waveform where the impulse sensitivity function (ISF) approaches zero, leading to reduced noise-to-PN conversion, even without excessive D-to-G voltage gain. Meantime, the introduced$V_{\mathrm {G2}}$enlarges the zero-current (ZC) zone in the output current waveform, thus improving the power efficiency. Two prototypes of VCO targeting room-temperature (RT) and cryogenic applications are designed and measured to verify the proposed architecture. The RT VCO achieves a frequency tuning range (FTR) from 9.37 to 10.86 GHz, delivering state-of-the-art PN of −143 dBc/Hz at a 10-MHz offset, and attaining a peak FoM of 198.9 dBc/Hz. The cryogenic VCO measured an average FoM of 210.2 dBc/Hz under sub-1 mW at 4.2 K.

Fields of Study & Subjects

Radio Frequency Integrated Circuit Design Advanced Power Amplifier Design Acoustic Wave Resonator Technologies

Publication details

Journal / source
IEEE Journal of Solid-State Circuits
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Volume
61
Issue
5
Pages
1860–1875
Publication date
3 February 2026