A 94.8-nW Battery-Free Intelligent Silicon Platform for Distributed Multimodal Sensing With Adaptive and Event-Driven Computing

This article presents an ultralow-power (ULP), battery-free intelligent silicon platform for distributed, multimodal sensing with adaptive, event-driven computing in edge devices. The proposed silicon platform incorporates hardware–software co-design in the implementation. At the algorithm level, a lightweight forward-forward (Lite-FF) algorithm is proposed to enable: 1) distributed model training with low-bitwidth operation and a small memory footprint and 2) event-driven feature transmission. At the circuit level, the digital compute-in-memory (CIM) architecture is employed to accelerate multiply-and-accumulate (MAC) operations with two key features for computation energy efficiency improvement: 1)a sparsity-adaptive input scheduler (SAIS) to skip redundant activation bit-level computations and 2) a sign-magnitude bit-significance accumulator (SM-BSA) to reduce bitline toggling by leveraging weight sparsity in sign-magnitude format. Fabricated in 65-nm CMOS, the silicon platform consumes 94.8 and 340.4nW in inference and training mode, respectively. Evaluated on a condition-based monitoring (CbM) task, the proposed framework can achieve a classification accuracy of 90.6% with dual-modal sensing while demonstrating the ability of on-chip training. The proposed compute engine can achieve a peak energy efficiency of 10.7 fJ/MAC at a 0.4-V supply voltage, outperforming the state-of-the-art nanowatt-class neural network (NN) accelerators by$1.76\times $.