A 40-nm Programmable Heterogeneous SoC With 5.625/0.85 MB RRAM/SRAM for Accelerating Neuro-Symbolic AI Models

Neuro-symbolic (NeSy) artificial intelligence (AI) integrates neural learning with symbolic reasoning to enable data-efficient, interpretable, and generalizable intelligence, making it a promising paradigm for human-like cognition. However, the heterogeneous and dynamic execution patterns of NeSy models pose fundamental challenges to conventional AI hardware, which is typically optimized for dense matrix operations. This article presents a fully programmable heterogeneous system-on-chip (SoC) fabricated in 40-nm CMOS, specifically designed to accelerate a wide range of NeSy workloads. The architecture features: 1) integrated resistive RAM (RRAM) and static random access memory (SRAM) neural-symbolic data paths; 2) ultra-dense (4.80 Mb/mm2), energy-efficient (0.247 pJ/b) RRAM macros with edge-triggered and prolonged sensing; 3) scheduler-informed power management; and 4) programming support for variable resolution, vector lengths, and batching. The SoC supports multiple NeSy paradigms and achieves up to 10.8 TOPS/W energy efficiency and$6.47\times $power reduction across reasoning benchmarks. This work demonstrates the first end-to-end silicon system for generalizable and efficient NeSy inference.