A 256-Point FFT Using Analog Floating-Point Computation With Post-Silicon Tuning

IEEE Journal of Solid-State Circuits 2026

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Authors: Jian-Fei Chang, Jungho Lee, Yi Shen, Sangbu Yun, Qirui Zhang, Dennis Sylvester, Hun‐Seok Kim, David Blaauw
DOI: 10.1109/jssc.2026.3659006
Cited by: 0
References: 35

Abstract

This article presents a 256-point fast Fourier transform (FFT) processor based on an analog floating-point computation framework. A novel floating-point analog multiply-and-accumulate (FP-AMAC) unit encodes mantissas as pulse widths with a 4-bit digital exponent and operates through integrate, pulse, and reset stages with accuracy enhancements, including node pre-charge and comparator delay compensation. Implemented in 22-nm CMOS, the processor achieves 0.71–1.13nJ/FFT at 1.53–1.94 GS/s, with a measured worst case output SNR of 31.37 dB, corresponding to a 12.3-bit fixed-point digital FFT. Post-silicon coarse-fine tuning and interpolation techniques ensure robust accuracy across process, voltage, and temperature (PVT) variations.

Fields of Study & Subjects

Analog and Mixed-Signal Circuit Design Low-power high-performance VLSI design Digital Filter Design and Implementation

Publication details

Journal / source
IEEE Journal of Solid-State Circuits
Volume
61
Issue
4
Pages
1477–1489
Publication date
10 February 2026
Language
EN