A 19-dBm 110--142-GHz CMOS Power Amplifier With Device-Centric Power Boosting and Dual-Coupled Slotline Combiner

In this article, a broadband power amplifier (PA) with an enhanced output power is proposed for the D-band frequency range. By deploying a new device-centric power model for cascode PA stages, it is first shown how an enhanced output power can be achieved by precisely choosing the device sizes in a cascode PA. Leveraging this finding, a novel three-transistor configuration is introduced where the additional transistor not only reuses the excess current due to the device size mismatch, but also helps increase the power gain. To further enhance the output power across a large bandwidth, a 4-way slotline-based dual-coupled differential power combiner (DCDPC) is proposed. An even-odd mode analysis is presented to evaluate the impedance matching performance of the DCDPC combiner. By combining the proposed PA stage and the broadband combiner, a three-stage PA is designed and fabricated in a 65-nm bulk CMOS process. The measured data show that a peak saturated output power of 19 dBm, a peak gain of 15.3dB, and a power added efficiency (PAE) of 5.3% is achieved. The PA is examined under various orders of amplitude modulations, where error vector magnitudes (EVMs) of${\leq } {-}21$dB have been consistently achieved. The fabricated chip occupies a core area of$0.99\times 0.48$mm2.