A Pseudo-Series Resonance CMOS Oscillator

This article presents a single-core, low-phase-noise (PN) digitally controlled oscillator (DCO) employing a pseudo-series resonance (pseudo-SR) technique with a transformer-based resonator. The proposed pseudo-SR resonator offers two key advantages: 1) a low impedance with a 180° phase shift at the impedance pole, emulating series resonance (SR) to enable single-stage oscillation and reduce the power overhead associated with conventional SR oscillators; and 2) flicker PN suppression by aligning the resonant frequencies of the series and parallel tanks, thereby balancing flicker noise exposure over the oscillation cycle. The tank characteristics are analyzed using closed-form derivations based on a transformer-equivalent model, while both thermal and flicker PN are evaluated through the impulse sensitivity function (ISF) framework. To eliminate the need for differential inputs required by conventional SR oscillators, a self-biased inverter is employed in place of an NMOS-only inverter. Fabricated in 28-nm CMOS, the prototype achieves PN of–128.7 and–124.1 dBc/Hz at a 1-MHz offset, with power consumption ($P_{\text {DC}}$) of 36.3 and 33.5 mW at 8.1 GHz ($f_{\min }$) and 9.9 GHz ($f_{\max }$), respectively. The flicker PN ($1/f^{3}$) corner lies between 230 and 380 kHz, and the oscillator core occupies an area of 0.16 mm2.