A 13.8% Speed-Enhanced 1 T Mask ROM by Algorithmically Signed Program Data on 3-nm Fin-FET Logic CMOS

As emerging applications increasingly demand higher computational power from embedded memories, achieving sufficient performance and timing margins has become a significant challenge. This article introduces an algorithmically signed mask ROM, which incorporates a sign column into the original read-only memory (ROM) bitcell array to address the tradeoff between access speed and read margin. By generating optimized sign bits for the given data, the proportion of “1”-bits programmed in each column is constrained within a certain narrow range, effectively mitigating the tradeoff. SPICE simulations and silicon measurements of a 1.8-Mbit signed ROM implemented on 3-nm Fin-FET logic CMOS demonstrate read access time improvements of 12.7% and 13.8%, respectively. The proposed signed ROM, which is compatible with compiler implementation, has the potential to significantly enhance the performance of embedded memories, particularly for emerging high-performance applications.