A 23.4--42.1-GHz Fractional-N Synthesizer With ADC-Based Direct Phase Digitization

IEEE Journal of Solid-State Circuits 2026

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Authors: Hao Xu, Yizhuo Wang, Ziyang Jiao, Guoyu Li, Yiyun Mao, Shuai Liu, Yan Liu, Jimiao Sang, Qi Guo, Long Kong, Na Yan
DOI: 10.1109/jssc.2026.3671094
Cited by: 0
References: 42

Abstract

A fractional-N digital phase-locked loop employs a novel analog-to-digital converter (ADC)-based phase detector (PD) to achieve direct phase digitization, thereby eliminating the need for a digital-to-time converter (DTC). The high PD gain reduces in-band phase noise, while its high linearity enables all-digital$\Sigma \Delta $quantization noise cancellation. Implemented with a dual-mode LC oscillator and followed by ultra-wideband frequency triplers, the complete frequency synthesizer covers a frequency range from 23.4 to 42.1 GHz, achieves a worst case integrated jitter of 175 fs, and consumes 25–30.5-mW power in 40-nm CMOS technology.

Fields of Study & Subjects

Advancements in PLL and VCO Technologies Radio Frequency Integrated Circuit Design Analog and Mixed-Signal Circuit Design

Publication details

Journal / source
IEEE Journal of Solid-State Circuits
Volume
61
Issue
8
Pages
4056–4070
Publication date
12 March 2026
Language
EN