A Low-Jitter Fractional- N Sampling PLL With Voltage-Domain Quantization-Error Cancellation Using a Nonlinearity-Replication Technique

This work presents a low-jitter, low-fractional-spur fractional-$N$digital sampling phase-locked loop (SPLL) that generates output frequencies from 10.4to 11.8GHz. Conventional fractional-$N$PLLs employ a digital-to-time converter (DTC) to cancel the quantization error (Q-error) of the delta-sigma modulator ($\Delta \Sigma $M). To address the nonlinearity (NL) of the DTC, i.e.,NLDTC, which degrades the rms jitter and spur performance, previous designs have employed either a digital pre-distortion (DPD) technique that requires significant hardware overhead or a highly linear DTC that inevitably increases design complexity. In contrast, this work presents a replica-NLdigital-to-analog converter (RNL-DAC) that intrinsically replicates theNLprofile of the sampling phase detector (SPD), thereby naturally canceling the$\Delta \Sigma $M Q-error with minimal design resources. This work also presents a complementary voltage comparator (VC) that accommodates a wide range of input voltages, thereby maintaining high sampling gain for low in-band phase-noise (PN). The proposed fractional-$N$SPLL was fabricated in a 40-nm CMOS process and consumed 15.3mW while generating an 11.1-GHz output signal from a 150-MHz reference. The measured rms jitter and fractional spur were 76fs and −65dBc, respectively, at a fractional-$N$frequency near 11.1GHz, demonstrating an excellent jitter-power figure of merit (FoM${}_{\mathrm {JIT}}$) despite its simple architecture.