An 18.3- μ W 108.3-dB DR Discrete-Time Delta-Sigma Modulator Using a Loop Filter Auto-Shift Technique

This article presents a discrete-time, third-order, single-loop, 17-level delta-sigma modulator (DSM) for high-dynamic-range sensor measurement applications, which employs a loop filter auto-shift (LFAS) technique. It uses an on-chip 1.5-bit Schmitt monitor to determine whether the input amplitude is large or small. The DSM automatically shifts to loop filter A for large input amplitudes to achieve a larger maximum stable amplitude (MSA) and shifts to loop filter B for small input amplitudes to reduce equivalent kT/C noise and in-band quantization noise (IBQN). The 1.5-bit successive-approximation-register (SAR) monitor, 17-level SAR quantizer, false trigger protection (FTP) module, capacitor compensation array, and pre-charge cascoded floating inverter amplifier (PFIA) support real-time shifting of the proposed DSM while ensuring good performance. The prototype DSM is designed and fabricated in a 180-nm CMOS process, achieving a 101.1-dB SNDR and a 108.3-dB dynamic range (DR) within a 3-kHz bandwidth, while consuming$18.3~\mu $W. With the help of the LFAS technique, the SNDR is improved by 5.65 dB at small input amplitudes. As a result, the Schreier figure of merit (FoM) for SNDR and DR is 183.2 and 190.4 dB, respectively.