STAR-SRAM: 16-bit Floating-Point SRAM-Based Digital Computing-in-Memory Macro in a 28 nm

A digital computing-in-memory (DCIM) macro emerges as a promising building block in a deep neural network (DNN) accelerator. To better support DNN workloads, circuit designers aim to improve three main metrics for macros: energy efficiency, compute density, and weight density. Improvements in those metrics directly translate into reduced energy consumption, shorter inference latency, and a smaller silicon footprint at the accelerator level. This article introduces STAR-SRAM, a DCIM macro designed for 16-bit brain floating-point (BF16) arithmetic. The macro is designed using a top-down approach. We started the design process with model-based parameter optimization, in which we determined the optimal design parameters that maximize the figure of merit (FoM) of a DCIM macro. Then, we developed several circuit techniques that further improve the FoM, including pre-multiply symmetric alignment, approximate multiplier circuits, and sparsity-aware wordline, clock, and input gating techniques. Fabricated in 28-nm CMOS, STAR-SRAM achieves the state-of-the-art FoM with up to 43.06 TFLOPS/W, 1.89 TFLOPS/mm2, and 400 Kb/mm2.