CMOS Compatible Low-loss Optical Tunnel Vias for 3D Photonic Integration

The dimensional limit of a single-mode waveguide cross-section is the fundamental roadblock of designing compact and large-scale planar photonic integrated circuits (PICs). The other limitation is the choice of waveguide core materials for designing various passive and active components for the application specific PICs. Fortunately, besides crystalline Si, plenty of other options of waveguide core materials such as epitaxially grown Ge, PECVD/LPCVD grown SiN, AlN, etc., are available for the utilization of advanced CMOS fabrication process compatible silicon photonics technology in silicon-on-insulator (SOI) platform. However, because of the absence of a suitably designed optical via, hybrid structure waveguide components and multi-layered three-dimensional PIC designs couldn't be effectively implemented till date. Here, we have proposed a low-loss compact optical tunnel via (OTV) design as a solution for 3D photonic integration. Using a standard Maxwell's equation solver, we have shown that the insertion loss of such a OTV design can be$< $0.1dB for a broad wavelength range of operations around 1550nm. We have also shown low-loss performance of such OTVs can be arrayed in designing complex PICs with hybrid waveguide components. The materials and design dimensions have been chosen carefully such that the proposed 3D-PICs can be easily manufactured in conventional CMOS foundries. We have also presented wavelength dependent loss (WDL) and polarization dependent loss (PDL) of various OTV designs for hybrid photonic interconnects using 3D-FDTD simulations.