Open DRAM Model—Part I: Cross-Layer Device, Array, and Circuit Analysis With BL-to-BL Coupling Mitigation for 4F 2 VCT DRAM

Dynamic random access memory (DRAM) scaling toward 4F2 vertical channel transistors (VCTs) fundamentally reshapes device, array, and circuit-level design tradeoffs. However, the lack of an open-source DRAM device model that is calibrated with recent industry trends prohibits broader innovations in the research community. In this work, we present an “Open DRAM Model” and showcase its application in cross-layer modeling and analysis for 4F2 VCT, spanning access-device electrostatics, array parasitics, sense margin, disturbance mechanisms, and peripheral integration under a CMOS-bonded-array (CBA) architecture. Based on publicly available disclosures, we construct TCAD-calibrated compact models and array-level frameworks. Our analysis reveals that while 4F2 VCTs benefit from reduced bitline (BL) capacitance (CBL) and increased initial sense margin, severe BL-to-BL direct coupling emerges as a first-order bottleneck and causes sensing failures. To address this, we evaluate two complementary mitigation strategies: 1) a cell-level partial (half) BL shielding scheme and 2) a circuit-level folded-like twisted BL sense amplifier (BLSA) topology. The proposed half-shield scheme achieves a balanced tradeoff between coupling suppression and CBL inflation, recovering positive sense margin under worst case ( $6.28\sigma $ ) variability. Furthermore, the folded-like twisted BLSA enables robust sensing even without cell-level shielding, while simultaneously improving sensing latency through effective differential coupling cancellation (nominal random cycle time: baseline D1b 21.5 ns, VCT 12.0 ns). By providing quantitative design guidelines, this work establishes a practical foundation for future 4F2 VCT DRAM technology pathfinding and system-technology co-optimization.