RF Design-Oriented ACM Model Generation Using Parametric Test and Machine Learning Regression in 28nm FD-SOI CMOS Technology

This paper presents a methodology for extracting design-oriented MOS transistor models from wafer-level parametric test (PT) data, enabling accurate post-fabrication circuit characterization that inherently accounts for process variability. Leveraging an advanced compact MOSFET (ACM) model, the approach employs a neural network regressor to predict critical RF transistor parameters, including DC characteristics, parasitic capacitances, and excess noise factor, from standard PT measurements routinely collected during production. The regressed parameters are gathered into a Verilog-A component that faithfully represents the electrical behavior of fabricated transistors, facilitating variability-aware simulation and performance analysis of RF integrated circuits without requiring additional test structures or any measurement overhead. Validation on 28 nm FD-SOI technology shows high prediction accuracy for NMOS devices, confirming the effectiveness of the methodology as a tool for supporting post-fabrication circuit simulations and process variability management.