CMM-H PMEM: Performance Characterization of CXL Large Capacity Persistent Memory

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Authors: Gongjin Sun, Mehdi Nik, Senthil Murugesapandian, Dongyang Li, Kwan Huen, Xuebin Yao, Caroline Kahn, Amir Beygi, Vitorio Cargnini, Ramdas Kachare
Cited by: 1
References: 7

Abstract

System architectures place memory in close proximity of CPU to achieve high performance. However, this directly and locally attached memory comes with constraints. Compute Express Link (CXL) enables robust memory disaggregation and thereby opens up new possibilities to address some of the direct-attached memory constraints. Samsung CMM-H is a CXL memory module that combines best aspects of DRAM and NAND in a novel architecture to provide a large capacity persistent memory (PMEM) solution. While NVMe SSDs offer capacity, they suffer from higher latency and inevitable write amplification when subjected to the fine-grained writes of data-intensive workloads. This paper presents a comprehensive characterization of the CMM-H PMEM solution. CMM-H device performance profile is compared to NVMe SSD. It achieves up to 100M random read IOPS, and latencies an order of magnitude lower for small I/Os. The large built-in DRAM cache is the architectural mechanism that enables this performance. The same mechanism also achieves a significant reduction in data written to the backend NAND thereby reducing write amplification factor (WAF). Lower WAF in turn provides benefits such as higher media endurance, lower power consumption, and lower latency. Direct measurement of real-world case studies demonstrates this mechanism reduces WAF by over 200x. This unique combination of high performance and significant write reduction establishes CMM-H as a compelling device solution in the PMEM landscape.

Fields of Study & Subjects

Ferroelectric and Negative Capacitance Devices Magnetic properties of thin films Parallel Computing and Optimization Techniques

Publication details

Journal / source
IEEE Computer Architecture Letters
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Volume
25
Issue
1
Pages
93–96
Publication date
1 January 2026