High-Fidelity and Noise-Resilient CNOT Gate Implementation Using Vertically Symmetric Fin-Based Architecture

We propose a vertically symmetric Fin-based architecture that enables high-fidelity CNOT gate operations with compact footprint. By tailoring the high-k oxide (OXT) and interlayer thickness (ILT), we effectively modulate the tunnel coupling and exchange interaction (J). A surrounding mid-gate provides additional control to finely tune the qubit states |↑⟩ and |↓⟩. In the presence of a gradient magnetic field, this design achieves a CNOT gate operation time of 45.3 ns. Our results are comparable to those reported in leading semiconductor CNOT-gate studies. To evaluate resilience to noise, the 1/f noise and Lorentzian spectra from interface traps are considered. Within these noise models, the proposed design achieves a gate fidelity of 99.81% and a dephasing timeT∗2= 27.68 μs, offering a scalable, CMOS-compatible pathway toward Si-based quantum processor.