Asymmetric Underlap–Overlap 2T Gain Cell Enabling Voltage-Sensing Readout With Minimized Capacitive Coupling
Abstract
This work introduces an asymmetric structure for a 2-transistor gain cell realized by a write transistor with gate-to-source/drain underlap and an overlapped read transistor. This asymmetric topology enables voltage sensing while substantially minimizing the word line to storage node capacitive coupling. Utilization of an underlapped write transistor reduces the storage node voltage disturbances during word line toggling. The overlapped structure of the read transistor increases the storage node capacitance, thereby improving the sense margin for robust voltage sensing. The concept is experimentally demonstrated using an amorphous oxide semiconductor-based asymmetric 2T gain cell, paving the way for monolithic 3D-integrated last-level cache at the back-end-of-line.
Fields of Study & Subjects
Thin-Film Transistor Technologies
Advanced Memory and Neural Computing
Advanced Data Storage Technologies
Publication details
- Journal / source
- IEEE Electron Device Letters
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Volume
- 47
- Issue
- 3
- Pages
- 522–525
- Publication date
- 1 January 2026