Demonstration of Gateless 1T Array Structure for High-Density DRAM Applications
Abstract
A gateless one-transistor DRAM (1T-DRAM) has been investigated due to its structural simplicity and simplified fabrication process. However, the absence of gate controllability raises concerns regarding array-level operation, necessitating experimental validation. In this paper, we experimentally demonstrate an 8 × 8 gateless 1T-DRAM array. By adopting a half-bias scheme, selective write and read operations are successfully achieved, while sneak currents are suppressed and stable retention characteristics (> 500 s) are maintained with large current sensing margin (> 60 μA). This reliable array operation highlights the gateless 1T-DRAM architecture as a practical pathway toward high-density DRAM applications.
Fields of Study & Subjects
Low-power high-performance VLSI design
Advancements in Semiconductor Devices and Circuit Design
Ferroelectric and Negative Capacitance Devices
Publication details
- Journal / source
- IEEE Electron Device Letters
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Volume
- 47
- Issue
- 3
- Pages
- 530–533
- Publication date
- 15 January 2026
- Language
- 영어