Demonstration of 2T1C 3D-DRAM With IGZO Vertical Channel Access Transistors for BEOL Monolithic Multi-Deck Stacking

This paper presents a 3D-NAND-like Two-Transistor-One-Capacitor (2T1C) 3D-DRAM architecture, which features Indium-Gallium-Zinc-Oxide (IGZO) Vertical-Channel-Access-Transistors (VCAT), vertical bit-line (VBL) wiring and multi-deck stackable capability with back-end-of-line (BEOL) monolithic integration. The vertical IGZO channel, formed simultaneously by atomic layer deposition (ALD) in recessed sidewall cavity, ensures uniform performance across layers, circumventing the degradation associated with layer-by-layer processing and enabling low-bit-cost scaling. We experimentally validated a 2-layer 2T1C structure, characterizing the VCAT electrical properties, read/write operations characteristics, and a retention time of 15.7s. 3D-TCAD simulations further assessed the parasitic capacitance and sense margin of the 2T1C array, confirming the excellent potential of this 3D-DRAM architecture for ultra-high-density Gb-scale DRAM applications.