Interlayer Co-Design Enabling a Large Memory Window and Robust Reliability in Ferroelectric Vertical Gate-All-Around FETs

In this letter, we present an epi-Si channel ferroelectric vertical gate-all-around (FEVGAA) FET featuring a gate and channel interlayer (G.IL/C.IL) co-design to achieve a wide memory window (MW) and robust reliability. The performance enhancement stems from two synergistic mechanisms: (1) gate-injected charges (QtG) induced by the G.IL, and (2) C.IL nitridation, which raises trap formation energy while introducing positive fixed charges to improve endurance, retention, and read-disturb immunity. Enabled by this strategy, a record MW of 3.5 V is realized, representing a 7.7X expansion compared to the reference FE-only device. The maximum ISPE slope also improves 8.8X. Notably, the device endures 5×104cycles with negligible Iondegradation at the large MW state. Endurance is further extended to 5×108cycles with a nanosecond-level high operating speed. Moreover, the retention loss after 10 years is only 2.8%. In addition, the device exhibits strong immunity to read disturb for 106cycles. This gate stack design expands the application of FEVGAA devices in high-density non-volatile memory.