Sub-0.2 V- V TH Cryo-CMOS Technology via Halo Implantation and Metal-Gate Engineering

IEEE Electron Device Letters 2026

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Authors: Chang He, Yue Xin, Xiaoyu Liu, Zewei Wang, Zhidong Tang, Longfei Yang, Xin Luo, Yumeng Yuan, Shuai Kong, Jianli Wang, Jianshi Tang, Xiaoxu Kang
+2 more Shaojian Hu, Xufeng Kou
DOI: 10.1109/led.2026.3683130
Cited by: 1
References: 30

Abstract

We report a 28-nm low-power cryogenic CMOS (Cryo-CMOS) technology for energy-efficient computing. The precise adjustments of metal-gate thickness and halo implants manage to compensate the threshold voltage (VTH) shift at low temperatures. The optimized cryogenic transistors are featured byVTHIDSAT>1.3 mA/μm) by 1.74×~3.71× compared to uLVT/RVT counterparts at 77 K. Combined with a reduced global device variability, the low-VTHdevices warrant a reliable sub-0.6V operation with an on/off ratio>107, reducing the total power consumption of the ring oscillator by 37% at 77 K.

Fields of Study & Subjects

Silicon and Solar Cell Technologies Thin-Film Transistor Technologies Semiconductor materials and interfaces

Publication details

Journal / source
IEEE Electron Device Letters
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Volume
47
Issue
6
Pages
1225–1228
Publication date
20 April 2026