Suppressing Interface Traps Density of Top-Gate MoS 2 Transistor via H 2 O Presoak for HfO 2
Abstract
Two-dimensional (2D) semiconductor materials, with their atomic thickness, effectively enhance electrostatic gate coupling and thus outperform traditional silicon in short-channel applications. Current top-gated field-effect transistors (FETs) based on molybdenum disulfide (MoS2) face challenges in forming a high-quality gate interface due to manufacturing process limitations. In this work, a H2O presoak ALD process is demonstrated to suppress the interface trap density (Dit) in MoS2devices. The optimized HfO2/MoS2gate stack presented a low Ditof 1.07 × 1010cm-2eV-1accurately assessed using the conductance method, which can satisfy the requirements for future high-performance digital ICs outlined by the IRDS.
Fields of Study & Subjects
Ferroelectric and Negative Capacitance Devices
Semiconductor materials and devices
Advancements in Semiconductor Devices and Circuit Design
Publication details
- Journal / source
- IEEE Electron Device Letters
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Volume
- 47
- Issue
- 6
- Pages
- 1137–1140
- Publication date
- 22 April 2026