Impact of Dual-Channel Communication for Wireless Interconnects of Chiplet-Based Architectures

The increasing demand for scalable and energy-efficient computing has driven the widespread adoption of chiplet-based architectures, where multiple smaller chiplets are integrated within a single package to overcome the limitations of monolithic System-on-Chip designs. However, a key challenge in these architectures is designing of the high-performance interconnects capable of efficiently handling both Intra-Chiplet and Inter-Chiplet communication. This paper studies the impact of wireless Interconnects against the wired counterpart in realizing reliable and efficient communication in chiplet based architectures. We also compare the advantages of the dual channel wireless interconnect over single channel wireless interconnect. Our study reveals that a token-passing protocol for wireless communication, employs a hybrid router equipped with two wireless transceivers provide better efficiency over a hybrid router equipped with single wireless transceiver. We evaluate the Average Packet Latency across varying Intra-Chiplet traffic loads ranging from 20% to 80% and injection rates to determine the saturation thresholds. Our simulation results demonstrate that the dual channel communication consistently outperforms the single channel setup, achieving significantly lower latency and supporting up to 2x higher injection rates before saturation. While dual channel communication effectively mitigates the wireless contention, it introduces the area and power overheads due to the additional wireless transceiver. However, the performance gains outweigh these overheads, making dual channel wireless interconnects a more scalable and performance-efficient solution for next-generation multi-chiplet platforms.