Reversible Logic-based RO-PUF Architecture with Enhanced Security Against Modeling and EM Side-channel Attacks

Protecting hardware devices from counterfeiting and attacks has led to the wide adoption of Physical Unclonable Function (PUF) as a hardware security primitive, which is used to generate unique circuit signatures. In this work, we proposed a Reversible-Logic (RL) system featuring a Ring Oscillator (RO) based PUF that enhances randomness, reliability, non-linearity, and resistance to machine-learning (ML), deep-learning (DL), and side channel attacks (SCA). The proposed design is implemented on an FPGA board and evaluated across different temperatures. Experimental results show that the proposed design achieves 49.70% uniformity, 49.99% uniqueness, and 50.90% bit aliasing at the room temperature. Also, Bit Error Rate (BER), Reliability, and Key error rate (KER) are calculated at various temperatures, and the significant results obtained are 0.002, 99.85%, and 0.046 at 40°C, respectively. In addition, the proposed RO-PUF successfully passes all 15 NIST randomness tests. Further ML and DL models were used to evaluate the modeling resistance, and the proposed design shows the best accuracy of 49.85%, which is close to a random guess, confirming the modeling resilience of our design. The proposed design was further evaluated under EM side channel analysis, demonstrating that it successfully conceals 96.85% information.