No HDL, No Problem: HLS-Generated Power Wasters for Fault Injection in Cloud FPGAs

Power wasters are a critical threat to cloud FPGAs. They induce voltage drops that lead to timing faults or complete denial of service. Previous methods for generating power wasters rely on low-level RTL modifications, including primitive-level structures and constraint manipulation. However, newer FPGA platforms such as Xilinx Versal restrict access to such low-level features, preventing traditional attack methods. In this work, we are the first to show that power wasters can still be created using only High-Level Synthesis (HLS), which is a standard development flow for cloud FPGAs. We demonstrate HLS-generated power wasters that can inject faults or crash the FPGA by applying overclocking and selected input patterns.