FP8GCN: An Edge-FPGA-Based Graph Convolutional Network Accelerator with FP8 Approximate Multipliers

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Authors: Shizhen Huang, Jiaren Peng, Yanxiang Zhu, Han Bao
Cited by: 0

Abstract

GCN accelerators often adopt pruning or quantization to reduce resource demands, yet energy efficiency remains a key challenge on FPGA platforms due to DSP-based matrix multiplications. Existing DSP-free approximate multipliers fail to strike a good trade-off between precision and efficiency. To overcome these, this letter presents the first FPGA-based FP8 approximate GCN accelerator, enabling both low precision loss and high energy efficiency. The proposed architecture is deployed on a Kintex-7 K325T FPGA, demonstrating that the accuracy loss of the approximate FP8 GCN model remains within 3%. While achieving average performance improvements of 12.9× (0.7-44.0×) and average energy savings of 169× (1.01-1010×) over CPUs, GPUs, and prior edge-FPGA-based accelerators.

Fields of Study & Subjects

Embedded Systems Design Techniques Advanced Neural Network Applications Low-power high-performance VLSI design

Publication details

Journal / source
IEEE Embedded Systems Letters
Pages
1–1
Publication date
1 January 2026
Language
EN