A Low-Latency Decoder for Sliding-Window FEC on ARM-FPGA Heterogeneous Systems

Sliding-window forward erasure correction (FEC) can provide reliable and low-latency packet transmissions over long-distance lossy channels such as those in space-air-ground integrated networks (SAGINs). However, software-based FEC decoding suffers from high latency, which has become a critical performance bottleneck. The bottleneck primarily stems from the intensive computational cost of Galois field arithmetic and the waiting delay of collecting packets to start decoding. To address this problem, this paper presents a heterogeneous FPGA-ARM implementation of a low-latency FEC decoder which can be naturally embedded in communication systems. We implement an on-the-fly Gaussian elimination (OF-GE) algorithm that processes packets upon arrival, together with multi-lane parallelized Galois field arthmetic based on dual-half-lookup-table that reduces BRAM consumption. Experimental results on a Zynq-7020 SoC demonstrate that the proposed decoder reduces 77% latency and achieves 3.4x decoding speed compared to software implementation.