XOR-TOPK : Efficient Top-K Selection Hardware Engine Based on Bitwise XOR Operation
Abstract
Top-k selection is one of the most widely used algorithms, aiming to identify the largest or smallestkelements in an input sequence. Numerous applications demand dedicated hardware to accelerate top-k operations. While prior works focus on algorithmic complexity, hardware cost depends heavily on operation types. This work exploits the low-cost nature of bitwise XOR operations to design a high-efficiency top-karchitecture, termed XOR-TOPK. The proposed design is modular and scalable, supporting various input sizes with low latency and area overhead. Compared with state-of-the-art designs, XOR-TOPK achieves up to 1.46×–19.7× reductions in area–delay and power–delay products for large-scale inputs. When integrated into a dynamic sparsity accelerator, it further reduces the area and latency of token selection stage, demonstrating strong potential for emerging applications.
Fields of Study & Subjects
Low-power high-performance VLSI design
Parallel Computing and Optimization Techniques
VLSI and FPGA Design Techniques
Publication details
- Journal / source
- IEEE Embedded Systems Letters
- Pages
- 1–1
- Publication date
- 1 January 2026
- Language
- EN