ML-Guided Branch Predictor Optimization for Embedded RISC-V SoCs

This paper explores branch predictor design for the CVA6 RISC-V core using gem5 simulation and machine learning-driven parameter optimization with comprehensive validation and cross-architecture analysis. Seven predictors are systematically evaluated using a multi-dimensional framework capturing performance, power, and embedded-specific metrics. Optuna-based tuning with Tree-structured Parzen Estimator explores 2,847 configurations to optimize energy-delay and area-performance trade-offs. Results show ML-optimized tournament predictors achieve 23.7% better performance than static predictors and 8.4% improvement over default configurations, while consuming 31% more power. The optimized bi-modal predictor emerges as optimal for power-constrained IoT applications, offering 94% of tournament predictor performance at 42% lower power consumption. Cross-architecture comparison with ARM Cortex-A53 reveals 9.3% better prediction accuracy for RISC-V with equivalent complexity. The framework provides validated workload-specific recommendations for embedded RISC-V systems with statistical confidence intervals and failure case analysis.