A Resource-Efficient VVC IME Architecture Using Buffered Aggregation and Bubble-Aware Comparison

VVC achieves higher compression efficiency than HEVC, but its Integer Motion Estimation (IME) incurs high hardware cost due to the complex partitioning structure introduced by the Quad-Tree Multi-Type Tree (QTMT). This letter presents a resource-efficient VVC IME architecture guided by QTMT-driven CU-distribution analysis. A 16×16 tiled processing structure is adopted as a balanced design point, while a Selectively Buffered Adder-Tree (SBAT) and a Bubble-Aware Comparator (BAC) are proposed to support multi-size SAD accumulation and comparator sharing under irregular CU distributions. Implemented on a Virtex-7 FPGA, the proposed design achieves 4K@60 fps using 34 151 LUTs, 22 315 FFs, and 109 BRAMs. In 180-nm RTL synthesis, it requires 94 kB of SRAM and 207.7k gates; when normalized to 65 nm, it achieves a hardware efficiency of 4 550.8 at 4K@114 fps. These results demonstrate that the proposed architecture reduces hardware cost while sustaining high-throughput VVC IME.