A Neuro-Stochastic Embedded Architecture for Energy-Adaptive and Error-Resilient Systems

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Authors: Yellapragada Charan Krishna, B. Naresh Kumar Reddy
Cited by: 1

Abstract

Traditional approximate computing architectures rely on static truncation and rigid mode switching fundamentally failing to adapt to transient data volatility and often incurring high post-correction overheads. To overcome these critical limitations a Neuro-Stochastic Adaptive Precision Multiplier (NS-APM) is proposed achieving reconfigurability at a continuous fine-grained level. By embedding a hardware-native, gate-level Neuro-Controller the architecture transitions from discrete binary truncation to a continuous probabilistic approximation. This neural agent dynamically controls novel Probabilistic Approximation Cells (PACs) adjusting decision thresholds on a cycle-by-cycle basis to stochastically sculpt the partial product matrix for optimal accuracy. Implemented on a Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit the design demonstrates a highly fluid Power-Performance-Accuracy navigation scaling dynamic power from 61.00 mW down to 14.52 mW across a 4-bit error budget range. Compared to static exact multipliers this methodology achieves up to a 96.9% reduction in energy-per-operation while maintaining a Mean Relative Error Distance as low as 0.0023%. The architecture successfully establishes a new paradigm for dynamic error-generation management by exploiting instantaneous data volatility.

Fields of Study & Subjects

Real-Time Systems Scheduling Embedded Systems Design Techniques Parallel Computing and Optimization Techniques

Publication details

Journal / source
IEEE Embedded Systems Letters
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Pages
1–1
Publication date
1 January 2026