A 6.5-to-11.5-GHz Frequency Doubler With Precalibration and Hybrid Edge-Combining Injection Locking Scoring 69.6-dBc Odd Harmonic Rejection in 65-nm CMOS

This letter describes a 6.5-to-11.5-GHz harmonic-rejection-enhanced frequency doubler (HRE-FD), in which hybrid edge-combining (EC) injection locking (IL) and cascaded injection-locked filtering are included to improve harmonic rejection. Before these circuits, precalibrations of the duty cycle skew and quadrature phase mismatch are introduced to further improve odd harmonic rejection and enhance its robustness. The proposed HRE-FD is fabricated in a 65-nm CMOS process and achieves a worst-case odd harmonic rejection of 69.6 dBc and a total harmonic rejection of 36.4 dBc. To the best of our knowledge, our HRE-FD has the highest odd harmonic rejection among state-of-the-art alternatives.