A Ring-Oscillator-Based Digital Harmonic-Mixing Fractional- N PLL

This paper presents a low-jitter digital harmonic-mixing fractional-N phase-locked loop (PLL) using a ring oscillator (RO). To extend the loop bandwidth, a mixer with unity gain in the phase domain is adopted, which helps suppress phase noise of the phase detector (PD) and delta-sigma modulator (DSM). Furthermore, to reduce mixing harmonics that would otherwise dominate the in-band jitter, the sinusoidal reference is buffered by a linear source follower, in contrast to the inverters used in other LC-oscillator-based harmonic-mixing PLLs. Implemented in 65 nm CMOS, the proposed PLL achieves 603.8 fs root-mean-square (RMS) jitter with a 100 MHz integration bandwidth. It occupies 0.12 mm2 of silicon area and consumes 12.72 mW of power.